The present invention relates to the design of integrated circuits, and more particularly, to the physical layout (i.e., placement) of logic cells in an integrated circuit design. An integrated circuit is fabricated by conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist”, which is a record of all the nets (or interconnections) between the cell pins. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns by an optical or electron beam generator. During fabrication, these patterns are used to pattern a wafer using a sequence of photolithographic steps. The process of converting the specifications of an electrical circuit into a layout is called the physical design.
Cell placement in integrated circuit fabrication involves a determination of where particular cells should optimally (or near optimally) be located on the surface of an integrated circuit device. Due to the large number of components and the details required by the fabrication process for a very large-scale integrated (VLSI) devices, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn-around time, and enhanced circuit performance. Several different programming languages have been created for electronic design automation (EDA), including Verilog, VHDL and TDML. A typical EDA system receives one or more high-level behavioral descriptions of the integrated circuit device, and translates this high-level design language description into netlists of various levels of abstraction.
Physical synthesis is prominent in the automated design of integrated circuits, such as high-performance processors and application-specific integrated circuits (ASICs). Physical synthesis is the process of concurrently optimizing placement, timing, power consumption, cross-talk effects and the like in an integrated circuit design. This comprehensive approach helps to eliminate iterations between circuit analysis and place-and-route. Physical synthesis has the ability to repower gates (changing their sizes), insert repeaters (buffers or reverters), clone gates or other combinatorial logic, etc., so that the area of logic in a design remains fluid. However, physical synthesis can take days to complete, and the computational requirements are increasing as designs are ever larger and more gates are needed to be placed.